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Created a rev 2 board

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This commit is contained in:
Molly Zaugg
2022-02-20 20:23:38 -05:00
parent 3fee1dcddc
commit 409bf6352d
19 changed files with 119588 additions and 14 deletions
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131
Libraries/REF102AU.lbr Normal file
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<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
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<deviceset name="REF102AU" prefix="U">
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<device name="" package="SOIC127P599X175-8N">
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<attribute name="Digi-Key_Part_Number" value="296-41381-2-ND"/>
<attribute name="MF" value="Texas Instruments"/>
<attribute name="Package" value="SOIC-8 Texas Instruments"/>
<attribute name="Description" value="
2.5-ppm/C drift, 10-V precision voltage reference 8-SOIC
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<attribute name="MP" value="REF102AU"/>
</technology>
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</devicesets>
</library>
</drawing>
</eagle>

139
Libraries/TL072ACD.lbr Normal file
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<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
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<deviceset name="TL072ACD" prefix="U">
<description> &lt;a href="https://pricing.snapeda.com/parts/TL072ACD/Texas%20Instruments/view-part?ref=eda"&gt;Check prices&lt;/a&gt;</description>
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<device name="" package="SOIC127P599X175-8N">
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<connect gate="A" pin="1IN+" pad="3"/>
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<connect gate="A" pin="1OUT" pad="1"/>
<connect gate="A" pin="2IN+" pad="5"/>
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<connect gate="A" pin="2OUT" pad="7"/>
<connect gate="A" pin="VCC+" pad="8"/>
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<attribute name="Package" value="SOIC-8 Texas Instruments"/>
<attribute name="MF" value="Texas Instruments"/>
<attribute name="Availability" value="Good"/>
<attribute name="Description" value="
Dual low-noise JFET-input improved offset operational amplifier 8-SOIC 0 to 70
"/>
<attribute name="MP" value="TL072ACD"/>
<attribute name="Price" value="None"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
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155
Libraries/TL074IDR.lbr Normal file
View File

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<!--This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0-->
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<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<packages>
<package name="SOIC127P600X175-14N">
<wire x1="-1.17" y1="-4.325" x2="1.17" y2="-4.325" width="0.127" layer="21"/>
<wire x1="-1.17" y1="4.325" x2="1.17" y2="4.325" width="0.127" layer="21"/>
<wire x1="-1.95" y1="4.325" x2="1.95" y2="4.325" width="0.127" layer="51"/>
<wire x1="1.95" y1="4.325" x2="1.95" y2="-4.325" width="0.127" layer="51"/>
<wire x1="1.95" y1="-4.325" x2="-1.95" y2="-4.325" width="0.127" layer="51"/>
<wire x1="-1.95" y1="-4.325" x2="-1.95" y2="4.325" width="0.127" layer="51"/>
<text x="-3.6" y="4.8" size="1.27" layer="25">&gt;NAME</text>
<text x="-3.6" y="-4.8" size="1.27" layer="27" align="top-left">&gt;VALUE</text>
<wire x1="-3.71" y1="4.575" x2="3.71" y2="4.575" width="0.05" layer="39"/>
<wire x1="3.71" y1="4.575" x2="3.71" y2="-4.575" width="0.05" layer="39"/>
<wire x1="3.71" y1="-4.575" x2="-3.71" y2="-4.575" width="0.05" layer="39"/>
<wire x1="-3.71" y1="-4.575" x2="-3.71" y2="4.575" width="0.05" layer="39"/>
<circle x="-4.05" y="4.1" radius="0.1" width="0.2" layer="21"/>
<circle x="-4.05" y="4.1" radius="0.1" width="0.2" layer="51"/>
<smd name="1" x="-2.475" y="3.81" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="2" x="-2.475" y="2.54" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="3" x="-2.475" y="1.27" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="4" x="-2.475" y="0" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="5" x="-2.475" y="-1.27" dx="1.97" dy="0.6" layer="1" roundness="50"/>
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<smd name="8" x="2.475" y="-3.81" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="9" x="2.475" y="-2.54" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="10" x="2.475" y="-1.27" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="11" x="2.475" y="0" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="12" x="2.475" y="1.27" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="13" x="2.475" y="2.54" dx="1.97" dy="0.6" layer="1" roundness="50"/>
<smd name="14" x="2.475" y="3.81" dx="1.97" dy="0.6" layer="1" roundness="50"/>
</package>
</packages>
<symbols>
<symbol name="TL074IDR">
<wire x1="-12.7" y1="17.78" x2="12.7" y2="17.78" width="0.41" layer="94"/>
<wire x1="12.7" y1="17.78" x2="12.7" y2="-17.78" width="0.41" layer="94"/>
<wire x1="12.7" y1="-17.78" x2="-12.7" y2="-17.78" width="0.41" layer="94"/>
<wire x1="-12.7" y1="-17.78" x2="-12.7" y2="17.78" width="0.41" layer="94"/>
<text x="-12.7" y="18.78" size="2.0828" layer="95" ratio="10" rot="SR0">&gt;NAME</text>
<text x="-12.7" y="-21.78" size="2.0828" layer="96" ratio="10" rot="SR0">&gt;VALUE</text>
<pin name="1IN+" x="-17.78" y="7.62" length="middle" direction="in"/>
<pin name="1IN-" x="-17.78" y="5.08" length="middle" direction="in"/>
<pin name="2IN+" x="-17.78" y="2.54" length="middle" direction="in"/>
<pin name="2IN-" x="-17.78" y="8.88178e-16" length="middle" direction="in"/>
<pin name="3IN+" x="-17.78" y="-2.54" length="middle" direction="in"/>
<pin name="3IN-" x="-17.78" y="-5.08" length="middle" direction="in"/>
<pin name="4IN+" x="-17.78" y="-7.62" length="middle" direction="in"/>
<pin name="4IN-" x="-17.78" y="-10.16" length="middle" direction="in"/>
<pin name="VCC+" x="17.78" y="15.24" length="middle" direction="pwr" rot="R180"/>
<pin name="VCC-" x="17.78" y="12.7" length="middle" direction="pwr" rot="R180"/>
<pin name="1OUT" x="17.78" y="7.62" length="middle" direction="out" rot="R180"/>
<pin name="2OUT" x="17.78" y="5.08" length="middle" direction="out" rot="R180"/>
<pin name="3OUT" x="17.78" y="2.54" length="middle" direction="out" rot="R180"/>
<pin name="4OUT" x="17.78" y="2.66454e-15" length="middle" direction="out" rot="R180"/>
</symbol>
</symbols>
<devicesets>
<deviceset name="TL074IDR" prefix="U">
<gates>
<gate name="A" symbol="TL074IDR" x="0" y="0"/>
</gates>
<devices>
<device name="" package="SOIC127P600X175-14N">
<connects>
<connect gate="A" pin="1IN+" pad="3"/>
<connect gate="A" pin="1IN-" pad="2"/>
<connect gate="A" pin="1OUT" pad="1"/>
<connect gate="A" pin="2IN+" pad="5"/>
<connect gate="A" pin="2IN-" pad="6"/>
<connect gate="A" pin="2OUT" pad="7"/>
<connect gate="A" pin="3IN+" pad="10"/>
<connect gate="A" pin="3IN-" pad="9"/>
<connect gate="A" pin="3OUT" pad="8"/>
<connect gate="A" pin="4IN+" pad="12"/>
<connect gate="A" pin="4IN-" pad="13"/>
<connect gate="A" pin="4OUT" pad="14"/>
<connect gate="A" pin="VCC+" pad="4"/>
<connect gate="A" pin="VCC-" pad="11"/>
</connects>
<technologies>
<technology name="">
<attribute name="Purchase-URL" value="https://pricing.snapeda.com/search/part/TL074IDR/?ref=eda"/>
<attribute name="Digi-Key_Part_Number" value="296-15000-1-ND"/>
<attribute name="MF" value="Texas Instruments"/>
<attribute name="Package" value="SOIC-14 Texas Instruments"/>
<attribute name="Description" value="
Quad Low-Noise JFET-Input General-Purpose Operational Amplifier 14-SOIC -40 to 85
"/>
<attribute name="MP" value="TL074IDR"/>
</technology>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
</eagle>

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<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.6.2">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="yes" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
<layer number="2" name="Route2" color="16" fill="1" visible="no" active="yes"/>
<layer number="3" name="Route3" color="17" fill="1" visible="no" active="yes"/>
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<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
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<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
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<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
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<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
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<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
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<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<packages>
<package name="SOIC127P590X140-14N" urn="urn:adsk.eagle:footprint:25599623/1">
<description>14-SOIC, 1.27 mm pitch, 5.90 mm span, 8.60 X 3.85 X 1.40 mm body
&lt;p&gt;14-pin SOIC package with 1.27 mm pitch, 5.90 mm span with body size 8.60 X 3.85 X 1.40 mm&lt;/p&gt;</description>
<circle x="-2.6788" y="4.6149" radius="0.25" width="0" layer="21"/>
<wire x1="-1.95" y1="4.4249" x2="1.95" y2="4.4249" width="0.12" layer="21"/>
<wire x1="-1.95" y1="-4.4249" x2="1.95" y2="-4.4249" width="0.12" layer="21"/>
<wire x1="1.95" y1="-4.35" x2="-1.95" y2="-4.35" width="0.12" layer="51"/>
<wire x1="-1.95" y1="-4.35" x2="-1.95" y2="4.35" width="0.12" layer="51"/>
<wire x1="-1.95" y1="4.35" x2="1.95" y2="4.35" width="0.12" layer="51"/>
<wire x1="1.95" y1="4.35" x2="1.95" y2="-4.35" width="0.12" layer="51"/>
<smd name="1" x="-2.4234" y="3.81" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="2" x="-2.4234" y="2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="3" x="-2.4234" y="1.27" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="4" x="-2.4234" y="0" dx="1.9685" dy="0.6019" layer="1"/>
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<smd name="13" x="2.4234" y="2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="14" x="2.4234" y="3.81" dx="1.9685" dy="0.6019" layer="1"/>
<text x="0" y="5.4999" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>
<text x="0" y="-5.0599" size="1.27" layer="27" align="top-center">&gt;VALUE</text>
</package>
</packages>
<packages3d>
<package3d name="SOIC127P590X140-14N" urn="urn:adsk.eagle:package:25599609/1" type="model">
<description>14-SOIC, 1.27 mm pitch, 5.90 mm span, 8.60 X 3.85 X 1.40 mm body
&lt;p&gt;14-pin SOIC package with 1.27 mm pitch, 5.90 mm span with body size 8.60 X 3.85 X 1.40 mm&lt;/p&gt;</description>
<packageinstances>
<packageinstance name="SOIC127P590X140-14N"/>
</packageinstances>
</package3d>
</packages3d>
<symbols>
<symbol name="V3046M">
<pin name="Q1C" x="-5.08" y="7.62" length="middle"/>
<pin name="Q1B" x="-5.08" y="5.08" length="middle"/>
<pin name="Q1/2E" x="-5.08" y="2.54" length="middle"/>
<pin name="Q2B" x="-5.08" y="0" length="middle"/>
<pin name="Q2C" x="-5.08" y="-2.54" length="middle"/>
<pin name="Q3B" x="-5.08" y="-5.08" length="middle"/>
<pin name="Q3E" x="-5.08" y="-7.62" length="middle"/>
<pin name="Q5C" x="22.86" y="7.62" length="middle" rot="R180"/>
<pin name="Q5E" x="22.86" y="5.08" length="middle" rot="R180"/>
<pin name="Q5B" x="22.86" y="2.54" length="middle" rot="R180"/>
<pin name="Q4C" x="22.86" y="0" length="middle" rot="R180"/>
<pin name="Q4E" x="22.86" y="-2.54" length="middle" rot="R180"/>
<pin name="Q4B" x="22.86" y="-5.08" length="middle" rot="R180"/>
<pin name="Q3C" x="22.86" y="-7.62" length="middle" rot="R180"/>
<wire x1="0" y1="10.16" x2="0" y2="-10.16" width="0.254" layer="94"/>
<wire x1="0" y1="-10.16" x2="17.78" y2="-10.16" width="0.254" layer="94"/>
<wire x1="17.78" y1="-10.16" x2="17.78" y2="10.16" width="0.254" layer="94"/>
<wire x1="17.78" y1="10.16" x2="0" y2="10.16" width="0.254" layer="94"/>
<text x="0" y="10.16" size="1.27" layer="95">&gt;NAME</text>
<text x="0" y="-12.7" size="1.27" layer="96">&gt;VALUE</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="V3046M" uservalue="yes">
<gates>
<gate name="G$1" symbol="V3046M" x="-5.08" y="0"/>
</gates>
<devices>
<device name="SOIC-14" package="SOIC127P590X140-14N">
<connects>
<connect gate="G$1" pin="Q1/2E" pad="3"/>
<connect gate="G$1" pin="Q1B" pad="2"/>
<connect gate="G$1" pin="Q1C" pad="1"/>
<connect gate="G$1" pin="Q2B" pad="4"/>
<connect gate="G$1" pin="Q2C" pad="5"/>
<connect gate="G$1" pin="Q3B" pad="6"/>
<connect gate="G$1" pin="Q3C" pad="8"/>
<connect gate="G$1" pin="Q3E" pad="7"/>
<connect gate="G$1" pin="Q4B" pad="9"/>
<connect gate="G$1" pin="Q4C" pad="11"/>
<connect gate="G$1" pin="Q4E" pad="10"/>
<connect gate="G$1" pin="Q5B" pad="12"/>
<connect gate="G$1" pin="Q5C" pad="14"/>
<connect gate="G$1" pin="Q5E" pad="13"/>
</connects>
<package3dinstances>
<package3dinstance package3d_urn="urn:adsk.eagle:package:25599609/1"/>
</package3dinstances>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
</note>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports the association of 3D packages
with devices in libraries, schematics, and board files. Those 3D
packages will not be understood (or retained) with this version.
</note>
</compatibility>
</eagle>

184
Libraries/V3046M.lbr Normal file
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@@ -0,0 +1,184 @@
<?xml version="1.0" encoding="utf-8"?>
<!DOCTYPE eagle SYSTEM "eagle.dtd">
<eagle version="9.6.1">
<drawing>
<settings>
<setting alwaysvectorfont="no"/>
<setting verticaltext="up"/>
</settings>
<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
<layers>
<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
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<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
<layer number="20" name="Dimension" color="24" fill="1" visible="yes" active="yes"/>
<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
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<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
<layer number="39" name="tKeepout" color="4" fill="11" visible="yes" active="yes"/>
<layer number="40" name="bKeepout" color="1" fill="11" visible="yes" active="yes"/>
<layer number="41" name="tRestrict" color="4" fill="10" visible="yes" active="yes"/>
<layer number="42" name="bRestrict" color="1" fill="10" visible="yes" active="yes"/>
<layer number="43" name="vRestrict" color="2" fill="10" visible="yes" active="yes"/>
<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
<layer number="47" name="Measures" color="7" fill="1" visible="no" active="yes"/>
<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
<layer number="88" name="SimResults" color="9" fill="1" visible="yes" active="yes"/>
<layer number="89" name="SimProbes" color="9" fill="1" visible="yes" active="yes"/>
<layer number="90" name="Modules" color="5" fill="1" visible="yes" active="yes"/>
<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
<layer number="93" name="Pins" color="2" fill="1" visible="yes" active="yes"/>
<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
</layers>
<library>
<packages>
<package name="SOIC127P590X140-14N" urn="urn:adsk.eagle:footprint:25599623/1">
<description>14-SOIC, 1.27 mm pitch, 5.90 mm span, 8.60 X 3.85 X 1.40 mm body
&lt;p&gt;14-pin SOIC package with 1.27 mm pitch, 5.90 mm span with body size 8.60 X 3.85 X 1.40 mm&lt;/p&gt;</description>
<circle x="-2.6788" y="4.6149" radius="0.25" width="0" layer="21"/>
<wire x1="-1.95" y1="4.4249" x2="1.95" y2="4.4249" width="0.12" layer="21"/>
<wire x1="-1.95" y1="-4.4249" x2="1.95" y2="-4.4249" width="0.12" layer="21"/>
<wire x1="1.95" y1="-4.35" x2="-1.95" y2="-4.35" width="0.12" layer="51"/>
<wire x1="-1.95" y1="-4.35" x2="-1.95" y2="4.35" width="0.12" layer="51"/>
<wire x1="-1.95" y1="4.35" x2="1.95" y2="4.35" width="0.12" layer="51"/>
<wire x1="1.95" y1="4.35" x2="1.95" y2="-4.35" width="0.12" layer="51"/>
<smd name="1" x="-2.4234" y="3.81" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="2" x="-2.4234" y="2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="3" x="-2.4234" y="1.27" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="4" x="-2.4234" y="0" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="5" x="-2.4234" y="-1.27" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="6" x="-2.4234" y="-2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="7" x="-2.4234" y="-3.81" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="8" x="2.4234" y="-3.81" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="9" x="2.4234" y="-2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="10" x="2.4234" y="-1.27" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="11" x="2.4234" y="0" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="12" x="2.4234" y="1.27" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="13" x="2.4234" y="2.54" dx="1.9685" dy="0.6019" layer="1"/>
<smd name="14" x="2.4234" y="3.81" dx="1.9685" dy="0.6019" layer="1"/>
<text x="0" y="5.4999" size="1.27" layer="25" align="bottom-center">&gt;NAME</text>
<text x="0" y="-5.0599" size="1.27" layer="27" align="top-center">&gt;VALUE</text>
</package>
</packages>
<packages3d>
<package3d name="SOIC127P590X140-14N" urn="urn:adsk.eagle:package:25599609/1" type="model">
<description>14-SOIC, 1.27 mm pitch, 5.90 mm span, 8.60 X 3.85 X 1.40 mm body
&lt;p&gt;14-pin SOIC package with 1.27 mm pitch, 5.90 mm span with body size 8.60 X 3.85 X 1.40 mm&lt;/p&gt;</description>
<packageinstances>
<packageinstance name="SOIC127P590X140-14N"/>
</packageinstances>
</package3d>
</packages3d>
<symbols>
<symbol name="V3046M">
<pin name="Q1C" x="0" y="7.62" length="middle" rot="R180"/>
<pin name="Q1B" x="0" y="5.08" length="middle" rot="R180"/>
<pin name="Q1E/Q2E" x="0" y="2.54" length="middle" rot="R180"/>
<pin name="Q2B" x="0" y="0" length="middle" rot="R180"/>
<pin name="Q2C" x="0" y="-2.54" length="middle" rot="R180"/>
<pin name="Q3B" x="0" y="-5.08" length="middle" rot="R180"/>
<pin name="Q3E" x="0" y="-7.62" length="middle" rot="R180"/>
<pin name="Q5C" x="10.16" y="7.62" length="middle"/>
<pin name="Q5E" x="10.16" y="5.08" length="middle"/>
<pin name="Q5B" x="10.16" y="2.54" length="middle"/>
<pin name="Q4C" x="10.16" y="0" length="middle"/>
<pin name="Q4E" x="10.16" y="-2.54" length="middle"/>
<pin name="Q4B" x="10.16" y="-5.08" length="middle"/>
<pin name="Q3C" x="10.16" y="-7.62" length="middle"/>
<wire x1="0" y1="10.16" x2="0" y2="-10.16" width="0.254" layer="94"/>
<wire x1="0" y1="-10.16" x2="10.16" y2="-10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="-10.16" x2="10.16" y2="10.16" width="0.254" layer="94"/>
<wire x1="10.16" y1="10.16" x2="0" y2="10.16" width="0.254" layer="94"/>
<text x="0" y="10.16" size="1.27" layer="95">&gt;NAME</text>
<text x="0" y="-12.7" size="1.27" layer="96">&gt;VALUE</text>
</symbol>
</symbols>
<devicesets>
<deviceset name="V3046M" uservalue="yes">
<gates>
<gate name="G$1" symbol="V3046M" x="-5.08" y="0"/>
</gates>
<devices>
<device name="SOIC-14" package="SOIC127P590X140-14N">
<connects>
<connect gate="G$1" pin="Q1B" pad="2"/>
<connect gate="G$1" pin="Q1C" pad="1"/>
<connect gate="G$1" pin="Q1E/Q2E" pad="3"/>
<connect gate="G$1" pin="Q2B" pad="4"/>
<connect gate="G$1" pin="Q2C" pad="5"/>
<connect gate="G$1" pin="Q3B" pad="6"/>
<connect gate="G$1" pin="Q3C" pad="8"/>
<connect gate="G$1" pin="Q3E" pad="7"/>
<connect gate="G$1" pin="Q4B" pad="9"/>
<connect gate="G$1" pin="Q4C" pad="11"/>
<connect gate="G$1" pin="Q4E" pad="10"/>
<connect gate="G$1" pin="Q5B" pad="12"/>
<connect gate="G$1" pin="Q5C" pad="14"/>
<connect gate="G$1" pin="Q5E" pad="13"/>
</connects>
<package3dinstances>
<package3dinstance package3d_urn="urn:adsk.eagle:package:25599609/1"/>
</package3dinstances>
<technologies>
<technology name=""/>
</technologies>
</device>
</devices>
</deviceset>
</devicesets>
</library>
</drawing>
<compatibility>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports URNs for individual library
assets (packages, symbols, and devices). The URNs of those assets
will not be understood (or retained) with this version.
</note>
<note version="8.3" severity="warning">
Since Version 8.3, EAGLE supports the association of 3D packages
with devices in libraries, schematics, and board files. Those 3D
packages will not be understood (or retained) with this version.
</note>
</compatibility>
</eagle>